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| publication release date: september, 2005 - 1 - revision a12 w6811 single-channel voiceband codec (5v analog, 3v digital) data sheet
w6811 publication release date: september, 2005 - 2 - revision a12 1. general description the w6811 is a general-purpose single channel pcm codec with pin-selectable -law or a-law companding. the device is compliant with the itu g. 712 specification. it operates off of separated analog (5v) and digital (3v) power supplies and is available in 24-pin pdip, sog, ssop, and tssop package options. functions performed include digiti zation and reconstruction of voice signals, and band limiting and smoothing filters required for pcm sys tems. the filters are compliant with itu g.712 specification. w6811 performance is specifi ed over the industrial temperature range of ?40 c to +85 c. the w6811 includes an on-chip precision voltage re ference and an additional power amplifier, capable of driving 300 loads differentially up to a level of 6.3v peak-to-peak. the analog section is fully differential, reducing noise and improving t he power supply rejection ratio. the data transfer protocol supports both long-frame and short-fram e synchronous communications for pcm applications, and idl and gci communications for isdn applications. w6811 accepts seven master clock rates between 256 khz and 4.096 mhz, and an on-chip pr e-scaler automatically determines the division ratio for the required internal clock. 2. features ? power supply: ? analog 4.5 ? 5.5v ? digital 2.7 ? 3.3v ? typical power dissipation of 25 mw, power-down mode of 0.5 w ? fully-differential analog circuit design ? on-chip precision reference of 1.575 v for a 0 dbm tlp at 600 ? push-pull power amplifiers with external gain adjustment with 300 load capability ? seven master clock rates of 256 khz to 4.096 mhz ? pin-selectable -law and a-law companding (compliant with itu g.711) ? codec a/d and d/a filtering compliant with itu g.712 ? industrial temperature range (?40 c to +85 c) ? four packages: 24-pin pdip, sog, ssop, and tssop ? pb-free / rohs package options available applications ? digital telephone systems ? central office equipment (gateways, switches, routers) ? pbx systems (gateways, switches) ? pabx/soho systems ? local loop card ? soho routers ? voip terminals ? enterprise phones ? isdn terminals ? analog line cards ? digital voice recorders w6811 publication release date: september, 2005 - 3 - revision a12 3. block diagram 256 khz, 512 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz & 4096 khz mclk 256 khz 8 khz 512 khz pre - scaler v dda v ssa power conditioning voltage reference v ag pui g.712 codec g.711 /a -law pao+ pao- pai ro - ao ai+ ai- /a - law tra ns mit pc m int erf ace re cei ve pc m int erf ace fst bclkt pcmt fsr bclkr pcmr v ref 256 khz, 512 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz & 4096 khz mclk 256 khz 8 khz pre - saler power conditioning voltage reference v ag g.712 codec g.711 /a -law ro /a - law g.712 codec g.711 /a -law ro /a - law transmit pcm interface receive pcm interface bclkt bclkt bclkr v v ddd v ssd w6811 publication release date: september, 2005 - 4 - revision a12 4. table of contents 1. general d escription ......................................................................................................... ........ 2 2. feat ures .................................................................................................................... ..................... 2 3. block diagra m............................................................................................................................... 3 4. table of cont ents ........................................................................................................... ........... 4 5. pin conf iguration ........................................................................................................... ............ 6 6. pin desc ription ............................................................................................................. ................ 7 7. functional descript ion............................................................................................................ 9 7.1. transmit path............................................................................................................. ................ 9 7.2. rece ive path.............................................................................................................. .............. 10 7.3. power managem ent.......................................................................................................... ....... 11 7.3.1. anal og supply ........................................................................................................... ..... 11 7.3.2. digi tal s upply .......................................................................................................... ....... 11 7.3.3. analog ground reference bypass................................................................................. 11 7.3.4. analog ground refe rence voltag e out put .................................................................... 11 7.4. pcm in terface ............................................................................................................. ............. 11 7.4.1. long fr ame sync ......................................................................................................... .. 12 7.4.2. short frame sync ........................................................................................................ .. 12 7.4.3. gci interface ........................................................................................................... ....... 12 7.4.4. idl interface ........................................................................................................... ........ 13 7.4.5. syst em ti ming........................................................................................................... ..... 13 8. timing diagra ms............................................................................................................. ............. 14 9. absolute maxi mum ratings.................................................................................................... 21 9.1. absolute ma ximum ratings ................................................................................................. ... 21 9.2. operating conditions ..................................................................................................... ......... 21 10. electrical ch aracteristics ............................................................................................... 22 10.1. general parame ters....................................................................................................... ........ 22 10.2. analog signal level and gain para meters............................................................................ 23 10.3. analog distortion an d noise parameters............................................................................... 24 10.4. analog input and output amplifier pa rameters ..................................................................... 25 10.5. digi tal i/o .............................................................................................................. ................. 27 10.5.1. -law encode dec ode characteri stics ........................................................................ 27 10.5.2. a-law encode deco de characteristics........................................................................ 28 10.5.3. pcm codes for zero and full scale ............................................................................ 29 10.5.4. pcm codes fo r 0dbm0 ou tput .................................................................................... 29 11. typical applic ation circuit ................................................................................................ .30 12. package spec ification ...................................................................................................... .... 32 12.1. 24l tssop ? 4.4x7.8mm .................................................................................................... .32 12.2. 24l so p ? 300m il......................................................................................................... ......... 33 12.3. 24l sso p ? 209m il ........................................................................................................ ....... 34 12.4. 24l pdip ? 300 mil ....................................................................................................... ......... 35 13. ordering information....................................................................................................... .... 36 14. version history ............................................................................................................ ........... 37 w6811 publication release date: september, 2005 - 5 - revision a12 5. pin configuration pdip/sop/ssop/tssop v ag ai+ ai - ao /a-law v ssa fst pcmt bclkt mclk v ssd n c v ref ro - pai pao - pao+ v dda fsr pcmi bclkr pui v ddd n c v ag ai+ ai - ao v ssa mclk v ssd n c v ref ro - pai pao - pao+ v dda fsr pcmr bclkr pui v ddd n c v ag 24 ai+ 23 ai - 22 ao 21 /a 20 v ssa 19 fsx 16 pcmo 15 bclkt 14 mclk 13 1 v ref 2 ro - 3 pai 4 pao - 5 pao+ 6 v dda 9 fsr 10 pcmi 11 bclkr 12 pui v ssd 17 8 v ddd n c 18 7 nc 24 23 22 21 20 19 16 15 14 13 1 2 3 4 5 6 9 10 11 12 17 8 18 7 w6811 publication release date: september, 2005 - 6 - revision a12 6. pin description pin name pin no. v dd * functionality v ref 1 a this pin is used to bypass the on-ch ip 2.5v voltage reference. it needs to be decoupled to v ssa through a 0.1 f ceramic decoupling capacitor. no external loads should be tied to this pin. ro- 2 a inverting output of the receive smoothi ng filter. this pin can typically drive a 2 k load to 1.575 volt peak referenced to the analog ground level. pai 3 a this pin is the inverting input to t he power amplifier. its dc level is at the v ag voltage. pao- 4 a inverting power amplifier output. this pin can drive a 300 load to 1.575 volt peak referenced to the v ag voltage level. pao+ 5 a non-inverting power amplifier output. this pin can drive a 300 load to 1.575 volt peak referenced to the v ag voltage level. v dda 6 a analog power supply. this pin should be decoupled to v ssa with a 0.1 f ceramic capacitor. nc 7 not connected v ddd 8 d digital power supply. this pin should be decoupled to v ssd with a 0.1 f ceramic capacitor. for correct operation, v ddd value should always be lower than v dda . fsr 9 d 8 khz frame sync input for the pcm receive section. this pin also selects channel 0 or channel 1 in the gci and idl modes. it can also be connected to the fst pin when transmit and receive are synchronous operations. pcmr 10 d pcm input data receive pin. the data needs to be synchronous with the fsr and bclkr pins. bclkr 11 d pcm receive bit clock input pin. th is pin also selects the interface mode. the gci mode is selected when this pin is tied to v ssd . the idl mode is selected when this pin is tied to v ddd . this pin can also be tied to the bclkt when transmit and receive are synchronous operations. pui 12 d power up input signal. when this pin is tied to v ddd , the part is powered up. when tied to v ssd , the part is powered down. mclk 13 d system master clock input. possi ble input frequencies are 256 khz, 512 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz & 4096 khz. for a better performance, it is recommended to have the mclk signal synchronous and aligned to the fst signal. this is a requirement in the case of 256 and 512 khz frequencies. bclkt 14 d pcm transmit bit clock input pin. pcmt 15 d pcm output data transmit pin. t he output data is synchronous with the fst and bclkt pins. fst 16 d 8 khz transmit frame sync inpu t. this pin synchronizes the transmit data bytes. w6811 publication release date: september, 2005 - 7 - revision a12 pin name pin no. v dd * functionality v ssd 17 d this is the digital supply ground. this pin should be connected to 0v. nc 18 not connected v ssa 19 a this is the analog supply ground. this pin should be connected to 0v. /a-law 20 d compander mode select pin. -law companding is selected when this pin is tied to v ddd . a-law companding is selected when this pin is tied to v ssd . ao 21 a analog output of the first gain stage in the transmit path. ai- 22 a inverting input of the first gain stage in the transmit path. ai+ 23 a non-inverting input of the fi rst gain stage in the transmit path. v ag 24 a mid-supply analog ground pin, which supplies a 2.5 volt reference voltage for all-analog signal processing. this pin should be decoupled to v ssa with a 0.01 f capacitor. this pin becomes high impedance when the chip is powered down. * these columns represent whether the pin is driv en by analog (?a?) or digital (?d?) power supply. w6811 publication release date: september, 2005 - 8 - revision a12 7. functional description w6811 is a single-rail, single channel pcm codec for voiceband applications. the codec complies with the specifications of the itu-t g.712 reco mmendation. the codec also includes a complete - law and a-law compander. the -law and a-law companders are designed to comply with the specifications of the itu-t g.711 recommendation. the block diagram in section 3 shows the main co mponents of the w6811. the chip consists of a pcm interface, which can process long and short frame sync formats, as well as gci and idl formats. the pre-scaler of the chip provides the inter nal clock signals and synchronizes the codec sample rate with the external frame sync frequency. the po wer conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. the main codec block diagram is shown in section 3. figure 7.1 the w6811 signal path pao+ pao 8 /a - cont ai+ ai - w /a- cont o ao + ro - - va g 7.1. t ransmit p ath the a-to-d path of the codec contains an analog input amplifier with externally configurable gain setting (see application examples in section 11). th e device has an input operational amplifier whose output is the input to the encoder section. if the input amplifier is not required for operation it can be powered down and bypassed. in that case a single ended input signal can be applied to the ao pin or the ai- pin. the ao pin becomes high input impedan ce when the input amplifier is powered down. the input amplifier can be powered down by connecting the ai+ pin to v dda or v ssa . the ao pin is selected as an input when ai+ is tied to v dda and the ai- pin is selected as an input when ai+ is tied to v ssa (see table 7.1). ant ant - aliasi filter = 3400 hz i - aliasi ng filter f c = 200 hz high pas filt smooth ng filter 2 hz filter 1 smooth ng v ag 8 /a control 8 /a- control + - - + + - pai ant ant high pass -aliasing filter - aliasing filter - filter filter smoothing filter filter filter filter smoothing receive path transmit path d/a converter + - - a/d converter f c = 3400hz f c = 3400hz c = 200hz f w6811 publication release date: september, 2005 - 9 - revision a12 ai+ input amplifier input v dda powered down ao 1.2 to v dda -1.2 powered up ai+, ai- v ssa powered down ai- table 7.1 input amplifier modes of operation when the input amplifier is powered down, the input signal at ao or ai- needs to be referenced to the analog ground voltage v ag . the output of the input amplifier is fed through a 3. 4 khz switched capacitor lo w pass filter to prevent aliasing of input signals above 4 khz, due to the sampling at 8 khz. the out put of the 3.4 khz low pass filter is filtered by a high pass filter with a 200 hz cut-off frequency. the filters are designed according to the recommendations in the g.712 itu-t specification. from the output of the high pass filter the signal is digitized. the signal is converted into a compressed 8-bit digital representation with either -law or a-law format. the -law or a-law format is pin-selectable through the /a-law pin. the compression format can be selected according to table 7.2. /a-law pin format v ssa a-law v dda -law table 7.2. pin-selectable compression format the digital 8-bit -law or a-law samples are fed to the pcm interface for serial transmission at the data rate supplied by the external bit clock bclkt. 7.2. r eceive p ath the 8-bit digital input samples for the d-to-a path are serially shifted in by the pcm interface and converted to parallel data bits. during every cycle of the frame sync fsr, the parallel data bits are fed through the pin-selectable -law or a-law expander and converted to analog samples. the mode of expansion is selected by the /a-law pin as shown in table 7.2. the analog samples are filtered by a low-pass smoothing filter with a 3.4 khz cut-off fr equency, according to the itu-t g.712 specification. a sin(x)/x compensation is integrated with the low pa ss smoothing filter. the output of this filter is buffered to provide the receive output signal ro-. th e ro- output can be externally connected to the pai pin to provide a differential output with high driving capability at t he pao+ and pao- pins. by using external resistors (see secti on 11 for examples), various gain se ttings of this output amplifier can be achieved. if the transmit power amplifier is not in use, it can be powered down by connecting pai to v dda . w6811 publication release date: september, 2005 - 10 - revision a12 7.3. p ower m anagement 7.3.1. analog supply the power supply for the analog part of the w6811 ne eds to be 5v +/- 10%. this supply voltage is connected to the v dda pin. the v dda pin needs to be decoupled to ground through a 0.1 f ceramic capacitor. 7.3.2. digital supply the power supply for the digital part of the w6811 needs to be 3v +/- 10%. this supply voltage is connected to the v ddd pin. the v ddd pin needs to be decoupled to ground through a 0.1 f ceramic capacitor. 7.3.3. analog ground reference bypass the system has an internal precision voltage reference which generates the 2.5v mid-supply analog ground voltage. this voltage needs to be decoupled to v ssa at the v ref pin through a 0.1 f ceramic capacitor. 7.3.4. analog ground reference voltage output the analog ground reference voltage is avail able for external reference at the v ag pin. this voltage needs to be decoupled to v ssa through a 0.01 f ceramic capacitor. the analog ground reference voltage is generated from the voltage on the v ref pin and is also used for the internal signal processing. 7.4. pcm i nterface the pcm interface is controlled by pins bclkr, fsr, bclkt & fst. the input data is received through the pcmr pin and the output data is transmitted through the pcmt pin. the modes of operation of the interface are shown in table 7.3. bclkr fsr interface mode 64 khz to 4.096 mhz 8 khz long or short frame sync v ssd v ssd isdn gci with active channel b1 v ssd v ddd isdn gci with active channel b2 v ddd v ssd isdn idl with active channel b1 v ddd v ddd isdn idl with active channel b2 table 7.3 pcm interface mode selections 7.4.1. long frame sync the long frame sync or short frame sync interface mode can be selected by connecting the bclkr or bclkt pin to a 64 khz to 4.096 mhz clock and co nnecting the fsr or fst pin to the 8 khz frame sync. the device synchronizes the data word fo r the pcm interface and the codec sample rate on the positive edge of the frame sync signal. it re cognizes a long frame sync when the fst pin is w6811 publication release date: september, 2005 - 11 - revision a12 held high for two consecutive falling edges of the bi t-clock at the bclkt pin. the length of the frame sync pulse can vary from frame to frame, as l ong as the positive frame sync edge occurs every 125 sec. during data transmission in the long frame sync mode, the transmit data pin pcmt will become low impedance when the frame sync signal fst is high or when the 8 bit data word is being transmitted. the transmit data pin pcmt will become high impedance when the frame sync signal fst becomes low while the data is transmitt ed or when half of the lsb is transmitted. the internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. to av oid bus collisions, the pcmt pin will be high impedance for two frame sync cycles after every powe r down state. more detailed timing information can be found in the interface timing section. 7.4.2. short frame sync the w6811 operates in the short frame sync mode w hen the frame sync signal at pin fst is high for one and only one falling edge of the bit-clock at th e bclkt pin. on the following rising edge of the bit-clock, the w6811 starts clocki ng out the data on the pcmt pin, which will also change from high to low impedance state. the data tr ansmit pin pcmt will go back to the high impedanc e state halfway through the lsb. the short frame sync operatio n of the w6811 is based on an 8-bit data word. when receiving data on the pcmr pin, the data is clocked in on the first falling edge after the falling edge that coincides with the frame sync signal. the internal decision logic will determine whether the next frame sync is a long or a short frame sync, ba sed on the previous frame sync pulse. to avoid bus collisions, the pcmt pin will be high impedance for two frame sync cycles after every power down state. more detailed timing information c an be found in the interface timing section. 7.4.3. general circuit interface (gci) the gci interface mode is selected when the bclkr pin is connected to v ssd for two or more frame sync cycles. it can be used as a 2b+d timing in terface in an isdn application. the gci interface consists of 4 pins : fsc (fst), dcl (bclkt), dout (pcmt) & din (pcmr). the fsr pin selects channel b1 or b2 for transmit and receive. data transitions occur on the positive edges of the data clock dcl. the frame sync positive edge is alig ned with the positive edge of the data clock dclk. the data rate is running half the speed of the bit-clock. the channels b1 and b2 are transmitted consecutively. therefore, channel b1 is transmi tted on the first 16 clock cycles of dcl and b2 is transmitted on the second 16 clock cycles of dcl. for more timing information, see the timing section. w6811 publication release date: september, 2005 - 12 - revision a12 7.4.4. interchip digital link (idl) the idl interface mode is selected when the bclkr pin is connected to v ddd for two or more frame sync cycles. it can be used as a 2b+d timing in terface in an isdn application. the idl interface consists of 4 pins : idl sync (fst), idl clk (b clkt), idl tx (pcmt) & idl rx (pcmr). the fsr pin selects channel b1 or b2 for transmit and receiv e. the data for channel b1 is transmitted on the first positive edge of the idl clk after the idl sync pulse. the idl sync pulse is one idl clk cycle long. the data for channel b2 is transmitted on the eleventh positive edge of the idl clk after the idl sync pulse. the data for channel b1 is received on the first negative edge of the idl clk after the idl sync pulse. the data for channel b2 is received on the eleventh negative edge of the idl clk after the idl sync pulse. the transmit signal pin idl tx becomes high impedance when not used for data transmission and also in the time slot of the unused channels. for more timing information, see the timing section. 7.4.5. system timing the system can work at 256 khz, 512 khz, 15 36 khz, 1544 khz, 2048 kh z, 2560 khz & 4096 khz master clock rates. the system clock is supp lied through the master clock input mclk and can be derived from the bit-clock if desired. an internal pre-scaler is used to generate a fixed 256 khz and an 8 khz sample clock for the internal codec. the pre-scaler measures the master clock frequency versus the frame sync frequency and sets the division ratio accordingly. if the frame sync is low for the entire frame sync period while the mclk and bclk pin clock signals are still present, the w6811 will enter the low power standby mode. another way to power down is to set the pui pin to low. when the system needs to be powered up again, the pui pin needs to be set to high and the frame sync pulse needs to be present. it will take two fr ame sync cycles before the pin pcmt will become low impedance. w6811 publication release date: september, 2005 - 13 - revision a12 8. timing diagrams fst bclkt d7 d6 d5 d4 d3 d2 d1 pcmt msb lsb t hid t bck d0 t bckh t bckl t fs t ftfh t ftrs t ftrh t hid t bdtd t fdtd 01 23 45 7 8 0 1 msb lsb fsr bclkr t bck d6 d5 d4 d3 d2 d1 d0 pcmr d7 t drh t drs t bckh t bckl t fs t frfh t frrs t frrh 01 23 45 67 8 0 1 6 mclk t ftrhm t ftrsm t mckh t mckl t mck t rise t fall t fsl t fsl figure 8.1 long frame sync pcm timing w6811 publication release date: september, 2005 - 14 - revision a12 symbol description min typ max unit 1/t fs fst, fsr frequenc y --- 8 --- khz t fsl fst / fsr minimum low width 1 t bck sec 1/t bck bclkt, bclkr frequency 64 --- 4096 khz t bckh bclkt, bclkr high pulse width 50 --- --- ns t bckl bclkt, bclkr low pulse width 50 --- --- ns t ftrh bclkt 0 falling edge to fst rising edge hold time 20 --- --- ns t ftrs fst rising edge to bclkt 1 falling edge setup time 80 --- --- ns t ftfh bclkt 2 falling edge to fst falling edge hold time 50 --- --- ns t fdtd fst rising edge to valid pcmt delay time --- --- 60 ns t bdtd bclkt rising edge to valid pcmt delay time --- --- 60 ns t hid delay time from the later of fst falling edge, or bclkt 8 falling edge to pcmt output high impedance 10 --- 60 ns t frrh bclkr 0 falling edge to fsr rising edge hold time 20 --- --- ns t frrs fsr rising edge to bclkr 1 falling edge setup time 80 --- --- ns t frfh bclkr 2 falling edge to fsr falling edge hold time 50 --- --- ns t drs valid pcmr to bclkr falling edge setup time 0 --- --- ns t drh pcmr hold time from bclkr falling edge 50 --- --- ns table 8.1 long frame sync pcm timing parameters 1 t fsl must be at least t bck w6811 publication release date: september, 2005 - 15 - revision a12 d7 d6 d5 d4 d3 d2 d1 msb lsb t bck d0 t bckh t bckl t fs t ftrs t ftrh t hid t bdtd 01 23 45 6 7 8 01 fst bclkt pcmt t bdtd t ftfh -1 t ftfs msb lsb t bck d6 d5 d4 d3 d2 d1 d0 d7 t drh t drs t bckh t bckl t fs t frrs t frrh 01 23 45 6 7 8 01 fsr bclkr pcmr t frfh -1 t frfs mclk t ftrhm t ftrsm t mckh t mckl t mck t rise t fall figure 8.2 short frame sync pcm timing w6811 publication release date: september, 2005 - 16 - revision a12 symbol description min typ max unit 1/t fs fst, fsr frequenc y --- 8 --- khz 1/t bck bclkt, bclkr frequency 64 --- 4096 khz t bckh bclkt, bclkr high pulse width 50 --- --- ns t bckl bclkt, bclkr low pulse width 50 --- --- ns t ftrh bclkt ?1 falling edge to fst rising edge hold time 20 --- --- ns t ftrs fst rising edge to bclkt 0 falling edge setup time 80 --- --- ns t ftfh bclkt 0 falling edge to fst falling edge hold time 50 --- --- ns t ftfs fst falling edge to bclkt 1 falling edge setup time 50 --- --- ns t bdtd bclkt rising edge to valid pcmt delay time 10 --- 60 ns t hid delay time from bclkt 8 falling edge to pcmt output high impedance 10 --- 60 ns t frrh bclkr ?1 falling edge to fsr rising edge hold time 20 --- --- ns t frrs fsr rising edge to bclkr 0 falling edge setup time 80 --- --- ns t frfh bclkr 0 falling edge to fsr falling edge hold time 50 --- --- ns t frfs fsr falling edge to bclkr 1 falling edge setup time 50 --- --- ns t drs valid pcmr to bclkr falling edge setup time 0 --- --- ns t drh pcmr hold time from bclkr falling edge 50 --- --- ns table 8.2 short frame sync pcm timing parameters w6811 publication release date: september, 2005 - 17 - revision a12 fst bclkt pcmt pcmr d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t fs t fsrh t fsfh t fsrs t bdtd t bdtd t bdtd t bdtd t hid t hid t drs t drs t drh t drh bch = 0 b1 channel bch = 1 b2 channel msb msb msb msb lsb lsb lsb lsb t bck t bckh t bckl -1 figure 8.3 idl pcm timing symbol description min typ max unit 1/t fs fst frequency --- 8 --- khz 1/t bck bclkt frequency 256 --- 4096 khz t bckh bclkt high pulse width 50 --- --- ns t bckl bclkt low pulse width 50 --- --- ns t fsrh bclkt ?1 falling edge to fst rising edge hold time 20 --- --- ns t fsrs fst rising edge to bclkt 0 falling edge setup time 60 --- --- ns t fsfh bclkt 0 falling edge to fst falling edge hold time 20 --- --- ns t bdtd bclkt rising edge to valid pcmt delay time 10 --- 60 ns t hid delay time from the bclkt 8 falling edge (b1 channel) or bclkt 18 falling edge (b2 channel) to pcmt output high impedance 10 --- 50 ns t drs valid pcmr to bclkt falling edge setup time 20 --- --- ns t drh pcmr hold time from bclkt falling edge 75 --- --- ns table 8.3 idl pcm timing parameters w6811 publication release date: september, 2005 - 18 - revision a12 fst bclkt pcmt pcmr d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 t fs t fdtd t bdtd t bdtd t bdtd t hid t hid t drs t drs t drh t drh bch = 0 b1 channel bch = 1 b2 channel msb msb msb msb lsb lsb lsb lsb t fsrh t fsfh t fsrs t bck t bckh t bckl 2345678910111213141516171819202122232425262728293031323334 10 figure 8.4 gci pcm timing symbol description min typ max unit 1/t fst fst frequency --- 8 --- khz 1/t bck bclkt frequency 512 --- 6176 khz t bckh bclkt high pulse width 50 --- --- ns t bckl bclkt low pulse width 50 --- --- ns t fsrh bclkt 0 falling edge to fst rising edge hold time 20 --- --- ns t fsrs fst rising edge to bclkt 1 falling edge setup time 60 --- --- ns t fsfh bclkt 1 falling edge to fst falling edge hold time 20 --- --- ns t fdtd fst rising edge to valid pcmt delay time --- --- 60 ns t bdtd bclkt rising edge to valid pcmt delay time --- --- 60 ns t hid delay time from the bclkt 16 falling edge (b1 channel) or bclkt 32 falling edge (b2 channel) to pcmt output high impedance 10 --- 50 ns t drs valid pcmr to bclkt rising edge setup time 20 --- --- ns t drh pcmr hold time from bclkt rising edge --- --- 60 ns table 8.4 gci pcm timing parameters w6811 publication release date: september, 2005 - 19 - revision a12 symbol description min typ max unit 1/t mck master clock frequency --- 256 512 1536 1544 2048 2560 4096 --- khz t mckh / t mck mclk duty cycle for 256 khz operation 45% 55% t mckh minimum pulse width high for mclk(512 khz or higher) 50 --- --- ns t mckl minimum pulse width low for mclk (512 khz or higher) 50 --- --- ns t ftrhm mclk falling edge to fst rising edge hold time 50 --- --- ns t ftrsm fst rising edge to mclk falling edge setup time 50 --- --- ns t rise rise time for all digital signals --- --- 50 ns t fall fall time for all digital signals --- --- 50 ns table 8.5 general pcm timing parameters w6811 publication release date: september, 2005 - 20 - revision a12 9. absolute maximum ratings 9.1. a bsolute m aximum r atings condition value junction temperature 150 0 c storage temperature range -65 0 c to +150 0 c voltage applied to any pin analog digital (v ssa - 0.3v) to (v dda + 0.3v) (v ssd - 0.3v) to (v ddd + 0.3v) voltage applied to any pin analog (input current limited to +/-20 ma) digital (v ssa ? 1.0v) to (v dda + 1.0v) (v ssd ? 1.0v) to (v ddd + 1.0v) v dda - v ssa ; v ddd - v ssd -0.5v to +6v v ddd ? v dda 2 < 0.3v 1. stresses above those listed may cause permanent damage to the device. exposure to the absolute maximum ratings may affect device reliability. functi onal operation is not implied at these conditions. 2. at any time, the digital power supply should not be higher the 0.3v from the analog power supply. 9.2. o perating c onditions condition value industrial operating temperature -40 0 c to +85 0 c analog supply voltage (v dda ) +4.5v to +5.5v digital supply voltage (v ddd ) +2.7v to +3.3v ground voltage (v ssa, v ssd ) 0v note : exposure to conditions beyond those listed un der absolute maximum ratings may adversely affect the life and reliability of the device. w6811 publication release date: september, 2005 - 21 - revision a12 10. electrical characteristics 10.1. g eneral p arameters symbo l parameters conditions min (2) typ (1) max (2) units v il input low voltage 0.5 v v ih input high voltage 2.2 v v ol pcmt output low voltage i ol = 1.6 ma 0.4 v v oh pcmt output high voltage i ol = -1.6 ma v ddd ? 0.5 v i dda i ddd v dda current (operating) -adc+dac pui = 1 fsx running mclk running 5.5 25 8 1000 ma a i sba i sbd v cca current (standby) pui = 1 fsx = 0 mclk running 200 0.2 500 100 na a i pda i pdd v cca current (power down) v ccd current (power down) pui = 0 pui = 0 200 200 500 500 na na i il input leakage current v ssd w6811 publication release date: september, 2005 - 23 - revision a12 10.3. a nalog d istortion and n oise p arameters v dda =5v 10%; v ssa =0v; t a =-40 c to +85 c; all analog signals referred to v ag ; mclk=bclk= 2.048 mhz; fst=fsr=8khz synchronous operation. transmit (a/d) receive (d/a) parameter sym. condition min. typ. ma x. min. typ. max. unit total distortion vs. level tone (1020 hz, -law, c-message weighted) d lt +3 dbm0 0 dbm0 to -30 dbm0 -40 dbm0 -45 dbm0 36 36 29 25 --- --- --- --- --- --- --- --- 34 36 30 25 --- --- --- --- --- --- --- --- dbc total distortion vs. level tone (1020 hz, a-law, psophometric weighted) d lta +3 dbm0 0 dbm0 to -30 dbm0 -40 dbm0 -45 dbm0 36 36 29 25 --- --- --- --- --- --- --- --- 34 36 30 25 --- --- --- --- --- --- --- --- dbp spurious out-of-band at ro- (300 hz to 3400 hz @ 0dbm0) d spo 4600 hz to 7600 hz 7600 hz to 8400 hz 8400 hz to 100000 hz --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- -30 -40 -30 db spurious in-band (700 hz to 1100 hz @ 0dbm0) d spi 300 to 3000 hz --- --- -47 --- --- -47 db intermodulation distortion (300 hz to 3400 hz ?4 to ?21 dbm0 d im two tones --- --- -41 --- --- -41 db crosstalk (1020 hz @ 0dbm0) d xt --- --- -75 --- --- -75 dbm0 absolute group delay abs 1200 hz --- --- 360 --- --- 240 sec group delay distortion (relative to group delay @ 1200 hz) d 500 hz 600 hz 1000 hz 2600 hz 2800 hz --- --- --- --- --- --- --- --- --- --- 750 380 130 130 750 --- --- --- --- --- --- --- --- --- --- 750 370 120 120 750 sec idle channel noise n idl -law; c-message a-law; psophometric --- --- --- --- 18 -68 --- --- --- --- 13 -78 dbrnc0 dbm0p w6811 publication release date: september, 2005 - 24 - revision a12 10.4. a nalog i nput and o utput a mplifier p arameters v dda =5v 10%; v ssa =0v; t a =-40 c to +85 c; all analog signals referred to v ag ; parameter sym. condition min. typ. max. unit. ai input offset voltage v off,ai ai+, ai- --- --- 25 mv ai input current i in,ai ai+, ai- --- 0.1 1.0 a ai input resistance r in,ai ai+, ai- to v ag 10 --- --- m ai input capacitance c in,ai ai+, ai- --- --- 10 pf ai common mode input voltage range v cm,ai ai+, ai- 1.2 --- v dda -1.2 v ai common mode rejection ratio cmrr ti ai+, ai- --- 60 --- db ai amp gain bandwidth product gbw ti ao, r ld 10k --- 2150 --- khz ai amp dc open loop gain g ti ao, r ld 10k --- 95 --- db ai amp equivalent input noise n ti c-message weighted --- -24 --- dbrnc ao output voltage range v tg r ld =10k to v ag r ld =2k to v ag 0.5 1.0 --- --- v dda -0.5 v dda -1.0 v load resistance r ldtgro ao, ro to v ag 2 --- --- k load capacitance c ldtgro ao, ro --- --- 100 pf ao & ro output current i out1 0.5 ao,ro- v dda -0.5 1.0 --- --- ma ro- output resistance r ro- ro-, 0 to 3400 hz --- 1 --- ro- output offset voltage v off,ro- ro- to v ag --- --- 25 mv analog ground voltage v ag relative to v ssa 2.429 2.5 2.573 v v ag output resistance r vag within 25mv change --- 2.5 12.5 power supply rejection ratio (0 to 100 khz to v dda , c- message) psrr transmit receive 30 30 80 75 --- --- dbc pai input offset voltage v off,pai pai --- --- 20 mv pai input current i in,pai pai --- 0.05 1.0 a pai input resistance r in,pai pai to v ag 10 --- --- m pai amp gain bandwidth product gbw pi pao- no load --- 1000 --- khz w6811 publication release date: september, 2005 - 25 - revision a12 parameter sym. condition min. typ. max. unit. output offset voltage v off,po pao+ to pao- --- --- 50 mv load resistance r ldpo pao+, pao- differentially 300 --- --- load capacitance c ldpo pao+, pao- differentially --- --- 1000 pf po output current i outpo 0.5 ao,ro- v dda -0.5 10.0 --- --- ma po output resistance r po pao+ to pao- --- 1 --- po differential gain g po r ld =300 , +3dbm0, 1 khz, pao+ to pao- -0.2 0 +0.2 db po differential signal to distortion c-message weighted d po z ld =300 z ld =100nf + 100 z ld =100nf + 20 45 --- --- 60 40 40 --- --- --- dbc po power supply rejection ratio (0 to 25 khz to v dda , differential out) psrr po 0 to 4 khz 4 to 25 khz 40 --- 55 40 --- --- db w6811 publication release date: september, 2005 - 26 - revision a12 10.5. d igital i/o 10.5.1. -law encode decode chatacteristics digital code d7 d6 d5 d4 d3 d2 d1 d0 normalized encode decision levels sign chord chord chord step step step step normalized decode levels 1 0 0 0 0 0 0 0 8031 : 1 0 0 0 1 1 1 1 4191 : 1 0 0 1 1 1 1 1 2079 : 1 0 1 0 1 1 1 1 1023 : 1 0 1 1 1 1 1 1 495 : 1 1 0 0 1 1 1 1 231 : 1 1 0 1 1 1 1 1 99 : 1 1 1 0 1 1 1 1 33 : 1 1 1 1 1 1 1 0 2 1 1 1 1 1 1 1 1 0 8159 7903 : 4319 4063 : 2143 2015 : 1055 991 : 511 479 : 239 223 : 103 95 : 35 31 : 3 1 0 notes: sign bit = 0 for negative values, sign bit = 1 for positive values w6811 publication release date: september, 2005 - 27 - revision a12 10.5.2. a-law encode decode characteristics digital code d7 d6 d5 d4 d3 d2 d1 d0 normalized encode decision levels sign chord chord chord step step step step normalized decode levels 1 0 1 0 1 0 1 0 4032 : 1 0 1 0 0 1 0 1 2112 : 1 0 1 1 0 1 0 1 1056 : 1 0 0 0 0 1 0 1 528 : 1 0 0 1 0 1 0 1 264 : 1 1 1 0 0 1 0 1 132 : 1 1 1 0 0 1 0 1 66 : 1 1 0 1 0 1 0 1 1 4096 3968 : 2048 2048 : 1088 1024 : 544 512 : 272 256 : 136 128 : 68 64 : 2 0 notes: 1. sign bit = 0 for negative values, sign bit = 1 for positive values 2. digital code includes inversion of all even number bits w6811 publication release date: september, 2005 - 28 - revision a12 10.5.3. pcm codes for zero and full scale -law a-law level sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) + full scale 1 000 0000 1 010 1010 + zero 1 111 1111 1 101 0101 - zero 0 111 1111 0 101 0101 - full scale 0 000 0000 0 010 1010 10.5.4. pcm codes for 0dbm0 output -law a-law sample sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) 1 0 001 1110 0 011 0100 2 0 000 1011 0 010 0001 3 0 000 1011 0 010 0001 4 0 001 1110 0 011 0100 5 1 001 1110 1 011 0100 6 1 000 1011 1 010 0001 7 1 000 1011 1 010 0001 8 1 001 1110 1 011 0100 w6811 publication release date: september, 2005 - 29 - revision a12 11. typical application circuit power control 1.0 uf - w6811 6 17 12 20 16 14 15 13 10 11 9 21 22 23 24 1 2 5 3 4 8 19 vdda vssd pui u/a fst bclkt pcmt mc lk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- vddd vssa 1.0 uf pcm in 27k differential audio in 2.048 mhz bit clock 27k 27k 0.1 uf - 27k 0.1 uf 27k pcm out 27k +5vdc +3vdc + 0.01 uf 0.1 uf 8 khz frame sy nc + differential audio out rl > 150 ohms mode select figure 11.1 typical circuit for differential analog i/o?s pcm out 1.0 uf 8 khz frame sy nc w6811 6 17 12 20 16 14 15 13 10 11 9 21 22 23 24 1 2 5 3 4 8 19 vdda vssd pui u/a fst bclkt pcmt mc lk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- vddd vssa 27k 0.1 uf +3vdc pcm in 1.0 uf 0.1 uf 0.01 uf audio in 27k audio out rl > 150 ohms 27k 27k 27k 2.048 mhz bit clock 100 uf +5vdc 27k 0.1 uf audio out rl > 2k ohms power control mode select figure 11.2 typical circuit for single ended analog i/o?s w6811 publication release date: september, 2005 - 30 - revision a12 100pf 3.9k microphone 0.1 uf 1.0 uf + 62k 1.5k 1k 1.0 uf 0.1 uf 1.5k 2.048 mhz bit clock w6811 6 17 12 20 16 14 15 13 10 11 9 21 22 23 24 1 2 5 3 4 8 19 vdda vssd pui u/a fst bclkt pcmt mc lk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- vddd vssa power control +5vdc 0.01 uf 27k 100pf speaker 8 khz frame sy nc 0.1 uf pcm out 3.9k electret pcm in 62k mode select 22 uf +3vdc 27k 27k figure 11.3 handset interface 0.1 uf pcm in w6811 6 17 12 20 16 14 15 13 10 11 9 21 22 23 24 1 2 5 3 4 8 19 vdda vssd pui u/a fst bclkt pcmt mc lk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- vddd vssa pcm out 600 ohm 1:1 27k 0.01 uf 2.048 mhz bit clock transformer 0.1 uf 27k 0.1 uf 8 khz frame sy nc 1.0 uf 27k +5vdc power control 27k 600 +3vdc mode select b1/b2 select figure 11.4 transformer interface circuit in gci mode w6811 publication release date: september, september, 2005 - 31 - revision a12 12. package specification 12.1. 24l tssop - 4.4x7.8 mm plastic thin shrink small outline package (tssop) dimensions dimension in mm dimension in inch symbol min nom max min nom max a 1.20 0.043 a1 0.05 0.15 0.002 0.006 a2 0.80 0.90 1.05 0.031 0.035 0.041 l 0.50 0.60 0.75 0.020 0.024 0.030 e 6.40 bsc. 0.252 bsc. he 4.30 4.40 4.50 0.169 0.173 0.177 d 7.70 7.80 7.90 0.303 0.307 0.311 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 l1 1.0 ref. 0.039 ref e 0.65 bsc. 0.026 bsc 01 0 8 0 8 w6811 publication release date: september, september, 2005 - 32 - revision a12 12.2. 24l sop-300 mil small outline package (sam e as sog & soic) dimensions dimensions in mm dimensions in inch symbol min max min max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 e 7.40 7.60 0.291 0.299 d 12.60 13.00 0.946 0.512 e 1.27 bsc. 0.050 bsc. h e 10.00 1065 0.394 0.419 y 0.10 0.004 l 0.40 1.27 0.016 0.050 0 0 8 0 8 l o c e h a1 a e b d seating plane y 0.25 gauge plane e 1 11 10 20 gauge plane seating plane w6811 publication release date: september, september, 2005 - 33 - revision a12 12.3. 24l ssop-209 mil shrink small outline package dimensions w6811 publication release date: september, september, 2005 - 34 - revision a12 12.4. 24l pdip ? 300 mil plastic dual inline package dimensions dimension in mm dimension in inch symbol min nom max min nom max a 4.45 0.175 a1 0.25 0.010 a2 3.18 3.30 3.43 0.125 0.130 0.135 b 0.41 0.46 0.56 0.016 0.018 0.022 b1 1.47 1.52 1.63 0.058 0.060 0.064 c 0.20 0.25 0.36 0.008 0.010 0.014 d 31.95 32.26 1.258 1.270 e 7.37 7.62 7.87 0.290 0.300 0.310 e1 6.43 6.55 6.68 0.253 0.258 0.263 e1 2.29 2.54 2.79 0.090 0.100 0.110 l 3.05 3.30 3.56 0.120 0.130 0.140 0 15 0 15 e a 8.38 8.89 9.40 0.330 0.350 0.370 s 2.29 0.090 e a 2 a c e base plane mounting plane 1 a 1 e l a s 1 e d 1 b b 24 1 12 13 w6811 publication release date: september, september, 2005 - 35 - revision a12 13. ordering information winbond part number description product family w6811 product w6811i _ _ package material: blank = standard package g = pb-free (rohs) package package type: w = 24-lead plastic thin small outline package (tssop) type 1 s = 24-lead plastic small outline package (sog/sop) r = 24-lead plastic small outline package (ssop) e = 24-lead plastic dual inline package (pdip) when ordering w6811 series devices, please refer to the following part numbers. part number w6811iw w6811is w6811ir w6811ie w6811iwg w6811isg w6811irg W6811IEG w6811 publication release date: september, september, 2005 - 36 - revision a12 14. version history version date page description a7 august 9, 2002 preliminary a8 september 26, 2002 a9 october 10, 2002 a10 october 23, 2003 34 changed the package dimension of the ssop24 package a11 april 2005 41 add important notice a12 september, 2005 2 11, 12 22 23 23 29, 30 35 added reference to pb-free rohs packaging capitalized logic high/low extended conditions on table 10.2. extended conditions on table 10.3. corrected idle channel noise min/max and units. improved application diagrams added g package ordering code w6811 publication release date: september, september, 2005 - 37 - revision a12 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical im plantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. the information contained in this da tasheet may be subject to change without notice. it is the responsibil ity of the customer to check the winbond usa website ( www.winbond-usa.com ) periodically for the latest version of this document, and an y errata sheets that ma y be g enerated |
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